Decreasing the Power-Clock Resonant Signal Central Voltage as a Mean for Power Reduction in Integrated Power and Clock Distribution Networks
| Author(s) |
Seyed Ebrahim Esmaeili, Abeer Imdoukh |
| Related to |
Faculty member |
Funded |
Yes |
| College |
CEAS |
Sponsor |
AUK |
| Course Name |
NA |
Amount in KWD |
1500 |
| Year |
NA |
DOI |
10.17485/IJST/v14i33.1820 |
| Status |
On-going Project |
Citation:
Esmaeili SE, Imdoukh A (2021) Decreasing the Power-Clock Resonant Signal Central Voltage as a Mean for Power Reduction in Integrated Power and Clock Distribution Networks. Indian Journal of Science and Technology.